1. Field of the Invention
This invention relates to an addition control system and more particularly to a system for controlling the addition (including the subtraction) of signed binary numbers expressed by N bits of the 2's complement notation. Sign control of an addend and an augend is carried out, and a corrective number (0, 1 or 2) is added to an adder circuit according to whether neither, one, or both the addend and the augend are applied to the adder circuit in the form of 1's complements, as a result of the sign control.
2. Description of the Prior Art
In the control of the addition of numbers represented with N bits of the 2's complement notation having sign bits, it is contemplated to effect the addition of an addend and an augend after their respective signed values have been sign controlled to be plus, minus, absolute value of minus of the absolute value. In certain cases, it is necessary that the addend and the augend be applied in the form of complements to a binary adder. Further, in the control of the addition of numbers represented with N bits having sign bits, it is desired to accurately detect the overflow state resulting from the addition.
In order prior art, in the case when an addition operation is to be performed after sign control, the addend and augend are transformed into N-bit numbers of the designated signs before the addition operation is performed. Consequently, many steps are required to effect the operation.